`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:08:35 11/26/2012 
// Design Name: 
// Module Name:    TRIG_DECIDE_UNIT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TRIG_DECIDE_UNIT #(parameter WIDTH=16, TRES=2, LOG_CYCLE=8, CYCLE=160)
(
		input clk,
		input rst,
		input strength_detect,
		input signed[WIDTH+WIDTH+1-1:0] coef_numerator,
		input signed[WIDTH+WIDTH-1:0] coef_denominator,
		output reg trig
		);
		
		reg signed[WIDTH+WIDTH+1-1:0] comp;
	
	always@(posedge clk or negedge rst)
	if(!rst)
		comp <= 0;
	else
		comp <= coef_denominator * TRES;
		
	always@(posedge clk or negedge rst)
		if(!rst)
			trig <= 0;
		else if(coef_numerator>comp & strength_detect)
			trig <= 1;
		else
			trig <= 0;
			

endmodule
